The present invention relates to a circuit configuration for driving a programmable link and to a use thereof in a mass memory chip.
In memory chips, for example synchronous dynamic random access memory (SRAMs), having a memory space of 256 megabytes, for example, replacement memory cells that can compensate for production-dictated failures of individual memory cells are usually provided for the purpose of providing redundancy. For this purpose, programmable links, also referred to as fuses, are provided, whose programming enables defective memory cells to be replaced by intact replacement cells. By way of example, a few thousand fuses may be provided in a RAM having a storage capacity of 256 MB.
In order to change over the programmable links from a low-impedance to a high-impedance state or vice versa, the programmable links are permanently changed over in a known manner either by an energy pulse in the form of a laser or by an electrical pulse. The electrical pulse may be, for example, a voltage pulse or a current pulse.
In this case, a distinction is made between fuses, which can be put into a non-conducting (high-impedance) state from a conducting (low-impedance) state by the energy pulse described, and antifuses, which can be changed from a non-conducting state to a conducting state by application of an energy pulse.
This so-called activation or blowing of fuses, which is a one-time, usually irreversible, operation which permanently changes the programmable link from a low-impedance to a high-impedance state or vice versa, has usually been effected hitherto by a laser prior to encapsulation of the memory chips with a housing. However, this is associated with the disadvantage that it is no longer possible to repair defective memory cells after encapsulation of the chips.
When fuses are blown by electrical pulses, it has usually been the case hitherto that a volatile memory in which the information that is to be permanently programmed is stored in a volatile manner is read and then the programmable links to be blown are externally addressed and selected by addresses. This procedure requires a high outlay. Moreover, the principle described takes a comparatively long time.
It is accordingly an object of the invention to provide a circuit configuration for driving a programmable link that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which permits rapid driving of the programmable link with a low outlay.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration. The circuit configuration contains a programmable link for permanent storage of a datum and a drive circuit. The drive circuit has a data input, a complementary data input, a drive circuit output coupled to the programmable link and outputting an energy pulse for activating the programmable link in a manner dependent on a data signal present at the data input, a first transistor having a control terminal connected to the data input, and a second transistor having a control terminal connected to the complementary data input. A volatile memory for storing a datum, is provided. The volatile memory contains an output outputting the data signal being a memory content of the volatile memory. The output is connected to the data input of the drive circuit for data communication, and the control terminal of the first transistor receives the data signal. The volatile memory has a complementary output outputting a complementary data signal being complementary to the data signal and connected to the complementary data input of the drive circuit. Therefore, the control terminal of the second transistor receives the complementary data signal.
The drive circuit provides an energy pulse that is suitable for the programming, activation or blowing of the programmable link. In this case, activation, programming or blowing of the programmable link is understood to be the permanent changeover of the programmable link from a low-impedance to a high-impedance state, or vice versa.
Such programmable links for the permanent storage of a datum, for example a single bit, are usually referred to as a fuse. Fuses that can be activated by an electrical energy pulse are also referred to as an e-fuse. The electrical energy pulse may be, for example, a current or voltage pulse.
In order, in a mass memory chip, for example an SDRAM, to be able to repair faults that occur or have been identified, that is to say defective memory cells, in real time, the volatile memory is required, using which defective memory cells can be replaced by redundant, intact cells by reprogramming. This is usually not possible with programmable links in real time, since programmable links cannot be blown within one clock cycle, which is just 10 ns, for example, given a clock rate of 100 MHz.
Rather, the permanent memory realized by the programmable link is suitable for storing the reprogramming, for example in memory chips. After a system having one or more memory chips has been switched off and switched on again, the already known information about programming with regard to defective memory cells should be able to be effected usually without renewed detection of defective memory cells and replacement thereof by redundant cells.
If an address of a defective memory cell to be replaced contains a plurality of bits, for example 25 bits, then it is possible, if the circuit configuration described is in each case suitable for the volatile and permanent storage of a single bit, to provide a plurality of circuit configurations described.
The principle described enables the direct driving of a programmable link using the drive circuit directly by a datum stored in the volatile memory. This results in a low outlay. Complicated reading from a volatile memory, which is also referred to as a fuse latch, and subsequent addressing of the assigned programmable link can be obviated in this case. Fast blowing or programming of programmable links, in particular in memory chips, is possible overall.
In one preferred embodiment of the invention, the output of the volatile memory is directly connected to the at least one data input of the drive circuit. The direct connection enables, on the one hand, a particularly simple circuit construction and, on the other hand, particularly fast blowing of programmable links.
In a further preferred embodiment of the present invention, the volatile memory contains a memory cell. In this case, the memory cell may be configured for the rapid storage of a datum. The output of the volatile memory, which may be directly connected to the at least one data input of the drive circuit, may be an output of the memory cell.
In a further preferred embodiment of the present invention, the memory cell has two inverters, which are coupled with negative feedback to form a self-latching latch. In this case, a respective input of one inverter may be coupled to an output of another inverter, whose input may be coupled to the output of the first inverter. This results in a self-latching latch. This enables a particularly simple construction of a memory cell, also called a latch, which, moreover, can be read from and written to particularly rapidly.
In a further preferred embodiment of the invention, the drive circuit has an activation input for feeding in an activation signal and a data input for feeding in a data signal. The data input may, as already described, be connected to the output of the volatile memory. In addition, an activation input may be provided, which generally enables a selection of the programmable link connected to the relevant drive circuit.
In a further preferred embodiment of the present invention, the drive circuit has an AND logic circuit, with the data input and the activation input for the AND combination of data signal and activation signal. In this case, an energy pulse is output on the output side of the drive circuit precisely when both data signal and activation signal, given positive circuit logic, in each case communicate a logic one.
In a further preferred embodiment of the present invention, the volatile memory has, in addition to the output, a complementary output, at which can be derived a data signal that is complementary to the data signal that can be derived at the output, and the drive circuit has, in addition to the at least one input, a complementary input connected to the complementary output. Input and complementary input are data inputs in this case. The signal that can be provided at the complementary input may be an inverse data signal. The complementary data signal that can be derived at the complementary output may be an inverse data signal.
In a further advantageous embodiment of the present invention, the complementary input is directly connected to the complementary output. For the transmission of complementary signals, the direct connection of data input and complementary input of the drive circuit to output and complementary output of the memory cell of the volatile memory may enable particularly fast blowing of the programmable link and also a particularly simple circuit construction.
In a further advantageous embodiment of the present invention, the drive circuit contains a blowing transistor, which, on the input side, is coupled to the at least one data input and also to a terminal for feeding in a blowing voltage and, on the output side, is coupled to the programmable link for the purpose of communicating a voltage pulse. The above-described energy pulse for blowing or activating the programmable link may be an electrical pulse, for example a voltage pulse described. The voltage pulse may advantageously be provided by the blowing transistor. By way of example, the above-described AND logic circuit may be connected on the output side to a control terminal of the blowing transistor. One terminal of the controlled path of the blowing transistor may be connected to the terminal for feeding in a blowing voltage and a further terminal of the blowing transistor may be directly connected to the programmable link.
In a further advantageous embodiment of the present invention, the drive circuit has a level boosting circuit, which, on the output side, is connected to an input of the blowing transistor. The level boosting circuit may be connected, by an input, for example to an output of the AND logic circuit. A higher blowing voltage may be provided by the level boosting circuit, if necessary for blowing the programmable link. In this case, the level boosting circuit increases the voltage level present on the input side, and provides a higher voltage level on the output side.
In a further preferred embodiment of the invention, the circuit configuration is constructed using CMOS circuit technology. This enables a particularly space-saving, current-saving and simple circuit construction.
In a further advantageous embodiment of the present invention, the circuit configuration is disposed in a mass memory chip. In this case, the circuit configuration described may be provided as a multiplicity thereof in the mass memory chip. In particular, it is possible to provide as many circuit configurations as there are programmable links. By way of example, 10,000 of the circuit configurations described may be provided in an SDRAM memory chip having a memory space of 512 MB.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for driving a programmable link, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.